1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device using an SOI substrate.
2. Description of the Background Art
FIG. 44 is a sectional view showing a structure of a conventional semiconductor device using an SOI substrate. The SOI substrate has a multilayer structure in which a silicon substrate 101, a BOX (Buried Oxide) layer 102 and a silicon layer 103 are provided in this order. Element isolating films 107a to 107c having bottom surfaces positioned above an upper surface of the BOX layer 102 are selectively formed in an upper surface of the silicon layer 103. Such an isolation will be hereinafter referred to as xe2x80x9ca partial isolationxe2x80x9d.
A PMOS transistor is formed in an element formation region defined by the element isolating films 107a and 107b. The PMOS transistor has p+ type source-drain regions 114a1 and 114a2 opposed to each other with an nxe2x88x92 type channel formation region 113a interposed therebetween, a gate structure 110a having a multilayer structure in which a gate insulating film 108 and a gate electrode 109a are provided in this order, and a side wall 111 formed on a side surface of the gate structure 110a. The source-drain regions 114a1 and 114a2 and the channel formation region 113a are formed in an nxe2x88x92 type well 112a. 
Moreover, an NMOS transistor is formed in an element formation region defined by the element isolating films 107b and 107c. The NMOS transistor has n+ type source-drain regions 114b1 and 114b2 opposed to each other with a pxe2x88x92 type channel formation region 113b interposed therebetween, a gate structure 110b having a multilayer structure in which a gate insulating film 108 and a gate electrode 109b are provided in this order, and a side wall 111 formed on a side surface of the gate structure 110b. The source-drain regions 114b1 and 114b2 and the channel formation region 113b are formed in a pxe2x88x92 type well 112b. 
According to the conventional semiconductor device shown in FIG. 44, the element isolating films 107a to 107c of a partial isolation type are formed in the upper surface of the silicon layer 103. Accordingly, electric potentials of the channel formation regions 113a and 113b can be externally fixed through the silicon layer 103 between the bottom surfaces of the element isolating films 107a to 107c and the upper surface of the BOX layer 102. In other words, a body contact can be taken.
However, the element isolating film 107b of the partial isolation type is also formed in a boundary portion of the nxe2x88x92 type well 112a and the pxe2x88x92 type well 112b. Therefore, the p+ type source-drain region 114a2 and the n+ type source-drain region 114b1 are electrically connected to each other through the nxe2x88x92 type well 112a and the pxe2x88x92 type well 112b which are provided under the element isolating film 107b. Consequently, there has been a problem in that a parasitic thyristor structure is formed in this portion so that latch up is generated.
In order to solve such a problem, it is an object of the present invention to obtain a method of manufacturing a semiconductor device which can take a body contact while electrically isolating an NMOS transistor and a PMOS transistor from each other through an insulator formed from an upper surface of a semiconductor layer to a bottom surface thereof (hereinafter referred to as xe2x80x9ca complete isolationxe2x80x9d) and can also contribute to microfabrication of an element.
A first aspect of the present invention is directed to a method of manufacturing a semiconductor device comprising the steps of (a) preparing a substrate having a multilayer structure in which an underlying layer and a semiconductor layer are provided, (b) selectively forming a first element isolating film which is not in contact with the underlying layer in a first main surface of the semiconductor layer on a side which is not in contact with the underlying layer, (c) forming an element having a conductor region which is positioned only above the first element isolating film on the first main surface of the semiconductor layer, (d) removing at least a part of the underlying layer, and (e) selectively forming a second element isolating film which is in contact with the first element isolating film below the conductor region in a second main surface of the semiconductor layer after the step (d).
A second aspect of the present invention is directed to a method of manufacturing a semiconductor device comprising the steps of (a) preparing a substrate having a multilayer structure in which an underlying layer and a semiconductor layer are provided, (b) selectively forming a first element isolating film which has a bottom portion shallower than bottoms of a first well of a first conductivity type and a second well of a second conductivity type and is not in contact with the underlying layer in a first main surface of the semiconductor layer on a side which is not in contact with the underlying layer in at least one of a first boundary portion between a region where the first well is to be formed and a region where the second well is to be formed and a second boundary portion between a region where a first semiconductor element is to be formed and a region where a second semiconductor element is to be formed in wells of the same conductivity type, (c) removing at least a part of the underlying layer, and (d) selectively forming a second element isolating film which is in contact with the first element isolating film in a second main surface of the semiconductor layer after the step (c).
A third aspect of the present invention is directed to a method of manufacturing a semiconductor device, comprising the steps of (a) preparing a substrate having a first main surface including a boundary between a first region and a second region, (b) selectively forming, in the first main surface of the substrate, a concave portion having a bottom surface which does not reach a second main surface of the substrate on a side opposite to the first main surface in a portion including the boundary, (c) forming a negative photoresist on a structure obtained at the step (b), (d) exposing the photoresist by using a photomask through which a phase of a light emitted above the first region and a phase of a light emitted above the second region are reverse to each other, (e) developing the photoresist after the step (d), (f) removing the substrate in a portion exposed at the step (e), thereby forming a through trench which penetrates from the bottom surface of the concave portion to the second main surface of the substrate, and (g) filling the concave portion and the through trench with an insulating film.
A fourth aspect of the present invention is directed to the method of manufacturing a semiconductor device according to the third aspect of the present invention, wherein the first region is a first well of a first conductivity type, the second region is a second well of a second conductivity type, the photoresist is exposed by using a phase-shifting mask having a shifter pattern in which a shifter for inverting a phase of an incident light is formed above the first region or above the second region at the step (d), and the shifter pattern is created based on design data in which layouts of the first and second wells in the substrate are described.
A fifth aspect of the present invention is directed to the method of manufacturing a semiconductor device according to the third aspect of the present invention, further comprising the step of (h) forming a semiconductor element having a conductor region on the substrate after the step (g), the concave portion being also formed below a region where the conductor region is to be formed at the step (b), and the photoresist being exposed by using a photomask having a mask pattern in which a light shielding film is formed above the region where the conductor region is to be formed at the step (d).
A sixth aspect of the present invention is directed to the method of manufacturing a semiconductor device according to the fifth aspect of the present invention, wherein the mask pattern is created based on design data in which a layout of the conductor region in the semiconductor element is described.
According to the first aspect of the present invention, the element isolating film of a complete isolation type having the first and second element isolating films is formed below the conductor region. Therefore, it is possible to avoid the generation of a parasitic capacitance between the conductor region and the semiconductor layer.
According to the second aspect of the present invention, the element isolating film of a complete isolation type having the first and second element isolating films is formed in at least one of the first boundary portion and the second boundary portion. Consequently, it is possible to avoid at least one of the influence of electrical connection of the first well and the second well through the semiconductor layer and the influence of electrical connection of the first semiconductor element and the second semiconductor element through the semiconductor layer.
According to the third aspect of the present invention, the through trench having a very small width can be formed. Therefore, it is possible to minimize the influence of the formation of a complete isolation having a great isolation width in the boundary portion between the first region and the second region, for example, a reduction in a channel width. Moreover, the microfabrication of the semiconductor device can also be obtained.
According to the fourth aspect of the present invention, the shifter pattern of the phase-shifting mask is created based on the design data created in the design stage. Consequently, it is possible to fabricate a phase-shifting mask having a desirable shifter pattern without creating any new data.
According to the fifth aspect of the present invention, the element isolating film of a complete isolation type having the insulating film filling the concave portion and the through trench can be formed below the conductor region. Consequently, it is possible to avoid the generation of a parasitic capacitance between the conductor region and the substrate.
According to the sixth aspect of the present invention, the mask pattern is created based on the design data created in the design stage. Consequently, it is possible to fabricate a photomask having a desirable mask pattern without creating any new data.